Here it is illustrated the best and easiest approach to calculate JFET self bias circuit. Self bias is one of the JFET biasing technique, the others being gate bias and voltage divider bias. The self bias method is used to bias JFET in its active region. It is usually used for JFET based small amplifier design. They are often found in front end of communication system to amplify small signals. The self bias sets more stable quiescent operating point(Q-point) than the gate bias but the bias point is not that extremely stable.
JFET self bias circuit diagram and Operation
The circuit diagram of self biased JFET is shown below.
In
the self biased circuit, a source resistor RS is added to the source
terminal. This source resistor RS sets a reverse gate to source voltage
\(V_{GS}\) at the gate. The gate is directly connected to the ground via
the gate resistor RG.
In JFET the gate current is zero and so the gate voltage is zero.
\(V_G=0\) --->(1)
Also because the gate current is zero the source current \(I_S\) is equal to drain current \(I_D\),
\(I_S=I_D\) --->(2)
The source voltage \(V_S\) is,
\(V_S = I_S R_S\) --->(3)
And from (6) we have,
\(V_S = I_D R_S\) --->(4)
The gate to source voltage is,
\(V_{GS} = V_G - V_S\) --->(5)
and because the gate voltage is zero from equation (5) we have,
\(V_{GS} = 0 - V_S\)
or, \(V_{GS} = -V_S\)
and from equation(6),
\(V_{GS} = - I_D R_S\) --->(6)
From equation(6) we can see that the gate to source is reversed biased due to the source resistor \(R_S\). This equation proves that by adding source resistor and grounding the gate we can have negative gate to source bias which reverse biases the gate to source junction of JFET.
A JFET when it is biased using self biasing technique is often used as an amplifier. For operation of a JFET as an amplifier the quiescent biasing point(Q-point) should be in active region in the drain characteristic curve and in the middle of the transconductance curve.
There are couple of ways to find quiescent biasing point for a JFET amplifier. There are mathematical methods and graphical methods. The graphical method gives more accurate Q-point. However the graphical method requires circuit simulation on computer to plot the graphs. So it is tedious and time consuming. There are also analytical and mathematical approach to calculate the biasing point but this may not give most accurate values. However the values calculated are close enough in order to use them. Here one such analytical method is provided.
To bias a JFET using self biasing method, we assume here that the quiescent drain current(\(I_{DQ}\))is half of the zero gate voltage drain current(\(I_{DSS}\)) that is,
\(I_{DQ} = \frac{I_{DSS}}{2}\) --->(7)
When this condition is used, we can derive that the quiescent gate to source voltage(\(V_{GSQ}\)) is approximately,
\(V_{GSQ} = \frac{V_{GS(off)}}{3.4}\) --->(8)
Now we can use these equation(7) and (8) to solve for the self biased JFET circuit.
Example Calculation
Let \(V_{DD}=5V\), \(I_{DSS}=10mA\) and \(V_{GS(off)}=-1.02V\)
Step 1: Find \(I_{DQ}\)
From (7), \(I_{DQ} = \frac{I_{DSS}}{2}=\frac{10mA}{2}=5mA\)
Step 2: Find \(V_{GSQ}\)
From(8), \(V_{GSQ} = \frac{V_{GS(off)}}{3.4}=\frac{-1.02V}{3.4}=-0.3V=-300mV\)
It also means \(V_S=300mV\)
Step 3: Find \(R_S\)
From (6), \(R_S=\frac{V_{GSQ}}{I_{DSQ}}=\frac{300mV}{5mA}=60\Omega\)
Step 4: Find \(R_D\)
Applying KVL on the output side of the circuit we have,
\(V_{DD} = I_{DQ}R_D + V_D\)
or, \(R_D = \frac{V_{DD}-V_D}{I_{DQ}}\)
let \(V_D=2V\) then,
\(R_D = \frac{V_{DD}-V_D}{I_{DQ}}=\frac{5V-2V}{5mA}=600\Omega\)
Optionally Step 5: Find \(V_{DSQ}\)
we have, \(V_{DSQ} = V_D - V_S=2V-0.3V=1.7V\)
The following shows the result in circuit simulator software.
We can see that the values from the circuit simulator is very close to the values calculated. The self bias circuit values for JFET amplifier can also be directly calculated using the online JFET biasing and amplifier design calculator.
Furthermore we can draw the load line on drain curve and transconductance curve and ensure that the JFET is biased properly in the active region. The Q-point from the above calculation is (\(V_{GSQ}\),\(I_{DQ}\)) =(300mV, 5mA). This calculated Q-point is shown in the transconductance curve below.
Similarly the Q-point on the drain curve is shown below.
As can be seen from the drain curve graph above, the Q-point lies in the active region and so the JFET can be operated as amplifying device.
