Here it is shown how to bias a JFET with voltage divider biasing method. Voltage divider biasing(VDB) is a popular biasing method for transistor which sets up a stable Q-point(Quiescent point) or operating point. Gate bias(Fixed bias) and self bias are other known methods for biasing a JFET. But they do not provide as much stable operating point like voltage divider biasing method. Gate bias is used for operating a JFET in ohmic region where it acts a variable resistor whereas self bias and voltage divider bias are used to bias a JFET in its active region where it acts as a constant current source. When JFET is biased in active region using VDB it is usually used as an amplifier. JFET are used in front end communication circuits as small signal amplifier and in oscillators in RF circuits. In this tutorial step by step guide is provided to make a complete JFET amplifier using voltage divider biasing method.
The circuit diagram of a JFET biased with voltage divider biasing technique and used as amplifier is shown below.
The voltage divider circuit consist of the potential divider circuit at the gate input formed by resistors R1 and R2, the drain resistor RD and the source resistor RS. The coupling capacitors CC1, CC2 and bypass capacitor CB, and the load resistor RL are not part of the voltage divider biasing circuit. The capacitors are used only for the ac signal input V1 at the gate. The load resistor RL is used here to show how to calculate the output coupling capacitor CC2.
The steps for biasing the JFET using the voltage divider method are as follows.
Step 1: Find value of \(V_{GS}\) and \(I_{DSS}\) from the JFET datasheet.
For example here we will be using MPF102 JFET which has the following values:
\(V_{GS(off)}=-1V\) and \(I_{DSS}=10mA\)
Step 2: Find \(V_{GS}\)
Here we take \(V_{GS}\) as half of \(V_{GS(off)}\)
\(V_{GS} = \frac{-V_{GS(off)}}{2} =-0.5V = -500mV\)
This also means, \(V_p = -V_{GS(off)} =-(-0.5V) = 0.5V = 500mV\)
Step 3: Find \(I_D\)
Since we have taken \(V_{GS}\) as half of \(V_{GS(off)}\), the \(I_D\) is,
\(I_D = \frac{I_{DSS}}{4}\)
and therefore, \(I_D = \frac{I_{DSS}}{4} = \frac{10mA}{4}=2.5mA\)
Step 4: Find \(V_G\)
To reverse bias the gate to source junction,
\(V_G = -V_{GS} = -(-0.5V) = 0.5V\)
Step 5: Find \(V_S\)
We have,
\(V_{GS}=V_G-V_S\)
so, \(V_S =V_G-V_{GS}=0.5V-(-0.5V)=1V\)
Step 6: Find \(R_1\)
Using voltage divider rule,
\(V_G = \frac{R_2}{R_1+R_2}V_{DD}\)
Rearranging for \(R_1\),
\(R_1 = R_2(\frac{V_{DD}}{V_G}-1)\)
Assume \(R_2 = 1k\Omega\) and \(V_{DD} = 5V\), and from step 5, \(V_G=0.5V\) and so,
\(R_1 = R_2(\frac{V_{DD}}{V_G}-1) = 1k\Omega(\frac{5V}{0.5V}-1)=9k\Omega\)
Step 7: Find \(R_S\)
\(R_S = \frac{V_S}{I_D}= \frac{1V}{2.5mA}=400\Omega\)
Step 8: Find \(R_D\)
Using KVL at the output loop of the circuit,
\(V_{DD}=I_DR_D+V_D\)
or, \(R_D=\frac{V_{DD}-V_D}{I_D}\)
Let \(V_D=2V\) then,
\(R_D=\frac{V_{DD}-V_D}{I_D}=\frac{5V-2V}{2.5mA}=1.2k\Omega\)
Step 9: Find \(V_{DS}\)
We have, \(V_{DS}=V_D-V_S=2V-1V=1V\)
Step 10: Find \(r_d\)
\(r_d = R_D || R_L = \frac{R_DR_L}{R_D+R_L}\)
Assume \(R_L=1k\Omega\) then,
\(r_d = \frac{R_DR_L}{R_D+R_L}=\frac{1.2k\Omega\times1k\Omega}{1.2k\Omega+1k\Omega}=545.45\Omega\)
Step 11: Find \(g_m\)
\(g_m = \frac{2 I_{DSS}}{V_p} (1-\frac{V_{GS}}{V_p})\)
or, \(g_m = \frac{2\times10mA}{0.5V} (1-\frac{(-0.5V)}{0.5V})=80mS\)
Step 12: Find voltage gain, \(A_v\)
\(A_v = g_m r_d\)
that is, \(A_v = 10mS \times 545.45\Omega = 43.64\)
Step 13: Find the input impedance, \(Z_i\)
\(Z_i = R_1||R_2||R_{GS}\)
But since \(R_{GS}\) is very large compared to \(R_1\) and \(R_2\) we have,
\(Z_i = \frac{R_1R_2}{R_1+R_2}=\frac{9k\Omega\times1k\Omega}{9k\Omega+1k\Omega}=900\Omega\)
Step 14: Find input coupling capacitor, \(CC_1\)
Let the input signal frequency be f=1kHz
\(CC_1 = \frac{10}{2\pi f Z_i}=\frac{10}{2\times3.14\times1kHz\times900\Omega}=1.77\mu F\)
Step 15: Find output impedance, \(Z_o\)
\(Z_o = R_D=1.2k\Omega\)
Step 16: Find output coupling capacitor, \(CC_2\)
\(CC_2 = \frac{10}{2\pi f Z_o}=\frac{10}{2\times3.14\times1kHz\times1.2k\Omega}=1.33\mu F\)
Step 17: Find the source bypass capacitor
\(CB = \frac{10}{2\pi f R_S}=\frac{10}{2\times3.14\times1kHz\times400\Omega}=3.98\mu F\)
The above values can be directly calculated using the online JFET Biasing & Amplfier Design Calculator.
The completed JFET amplifier with voltage divider bias is shown below.
The following circuit shows the measured current and voltages which is in agreement with the assumed and calculated values above.
The following shows the input and output signal waveform from the JFET amplifier.
The process of designing JFET amplifier with voltage divider biasing method is illustrated in the following video tutorial.
