Voltage Divider Biased D-MOSFET Amplifier Design

 Voltage divider biasing is one of several methods to bias a Depletion MOSFET transistor. It provides a stable operating point or Q-point for the transistor. In this method, a voltage divider circuit consisting of two resistors are connected to the gate that biases the gate voltage(gate to source voltage) for specific biasing point in the active region. A depletion MOSFET biased in active region can be used as an amplifier. Here it is shown how to bias a depletion MOSFET using voltage divider biasing method.

The following shows the circuit diagram of a voltage divider biased depletion MOSFET amplifier.

voltage divider biased delpletion MOSFET amplifier circuit diagram

The steps to bias D-MOSFET using voltage divider biasing method are as follows.

Step 1: Select circuit power supply voltage, the drain voltage and the input signal frequency.

Here we will use the following,

\(V_{DD}=5V\)

\(V_D=2.5V\)

\(f=22KHz\) 

Step 2: Find value of \(V_{GS}\) and \(I_{DSS}\) from the D-MOSFET datasheet.

For example here we will be using LND150 N-channel D-MOSFET for which the following values are used.

\(V_{GS(off)}=-2.2V\) and \(I_{DSS}=2.34mA\)

Step 3: Determine \(I_D\) and \(V_{GS}\)

Here we will assume that \(I_D\) is,

\(I_D = \frac{I_{DSS}}{2}\)

therefore, \(I_D = \frac{I_{DSS}}{2} = \frac{2.34mA}{2}=1.11mA\)

Since we have taken \(I_D\) to be half of \(I_{DSS}\) we have,

\(V_{GS} = \frac{-V_{GS(off)}}{3.4}\)

This can be derived by solving the transconductance equation.

So, \(V_{GS} = \frac{V_{GS(off)}}{3.4} =--0.65V = -650mV\)

This also means, \(V_p = -V_{GS(off)} =-(-0.65V) = 0.65V = 650mV\)

Step 4: Find \(V_G\)

To reverse bias the gate to source junction,

\(V_G = -V_{GS} = -(-0.65V) = 0.65V=650mV\)

Step 5: Find \(R_1\)

Using voltage divider rule, we have,

\(V_G = \frac{R_2}{R_1+R_2}V_{DD}\) 

Rearranging for \(R_1\),

\(R_1 = R_2(\frac{V_{DD}}{V_G}-1)\)

Assume \(R_2 = 10k\Omega\) and \(V_{DD} = 5V\), and from step 4, \(V_G=0.65V\) and so,

\(R_1 = R_2(\frac{V_{DD}}{V_G}-1) = 10k\Omega(\frac{5V}{0.65V}-1)=67.27k\Omega\)

Step 6: Find \(V_S\)

We have,

\(V_{GS}=V_G-V_S\)

so, \(V_S =V_G-V_{GS}=0.65V-(-0.65V)=1.3V\)

Step 7: Find \(R_S\)

\(R_S = \frac{V_S}{I_D}= \frac{1.3V}{1.11mA}=1.1k\Omega\)

Step 8: Find \(R_D\)

Using KVL at the output loop of the circuit,

\(V_{DD}=I_DR_D+V_D\)

or, \(R_D=\frac{V_{DD}-V_D}{I_D}\)

 Let \(V_D=2V\) then,

 \(R_D=\frac{V_{DD}-V_D}{I_D}=\frac{5V-2.5V}{1.11mA}=2.14k\Omega\)

Step 9: Find \(V_{DS}\)

We have, \(V_{DS}=V_D-V_S=2.5V-1.3V=1.2V\)

Step 10: Find \(r_d\)

\(r_d = R_D || R_L = \frac{R_DR_L}{R_D+R_L}\)

Assume \(R_L=1k\Omega\) then,

\(r_d = \frac{R_DR_L}{R_D+R_L}=\frac{2.14k\Omega\times1k\Omega}{2.14k\Omega+1k\Omega}=681.20\Omega\)

Step 11: Find \(g_m\)

\(g_m = \frac{2 I_{DSS}}{V_p} (1-\frac{V_{GS}}{V_{GS(off)}})\) 

or, \(g_m = \frac{2\times2.34mA}{0.65V} (1-\frac{(-0.65V)}{-2.2V})=5.11mS\) 

Step 12: Find voltage gain, \(A_v\)

\(A_v = g_m r_d\)

that is, \(A_v = 5.11mS \times 681.20\Omega = 3.48\)

Step 13: Find the input impedance, \(Z_i\)

\(Z_i = R_1||R_2\)

\(Z_i = \frac{R_1R_2}{R_1+R_2}=\frac{67.27k\Omega\times10k\Omega}{67.27k\Omega+10k\Omega}=8.71k\Omega\)

Step 14: Find input coupling capacitor, \(CC_1\)

\(CC_1 = \frac{10}{2\pi f Z_i}=\frac{10}{2 \times 3.14\times 22kHz \times 8.71k\Omega}=8.31nF\)

Step 15: Find output impedance, \(Z_o\)

\(Z_o = R_D=2.14k\Omega\)

Step 16: Find output coupling capacitor, \(CC_2\)

\(CC_2 = \frac{10}{2\pi f Z_o}=\frac{10}{2\times3.14\times1kHz\times1.2k\Omega}=1.33\mu F\)  

Step 17: Find the source bypass capacitor

\(CB = \frac{10}{2\pi f R_S}=\frac{10}{2 \times 3.14\times 22kHz \times 1.11k\Omega}=65.44nF\) 

So in this way we can calculate the current and voltages, the biasing resistor values, the coupling capacitors and the bypass capacitor value of a voltage divider biased depletion MOSFET amplifier. These values can also be directly computed using the online Depletion MOSFET Biasing & Amplifier Design Calculator.

The completed circuit with the calculated values above is shown below.

voltage divider biased delpletion MOSFET amplifier circuit diagram

We can verify the calculated values using circuit simulator like Proteus which is shown below.

VDB biased D-MOSFET Circuit Simulation

So in this tutorial we showed how to bias a depletion MOSFET using voltage divider biasing method. There are also other biasing methods. The following are other D-MOSFET biasing tutorials:

- Zero Gate Biased Depletion MOSFET Amplifier Design Example

- How to bias Depletion MOSFET with fixed gate biasing method 

- Quick way to design Self Biased Depletion MOSFET with Online Calculator


 

 


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